During the manufacturing of semiconductor devices a multiplicity of layers is deposited on a substrate and subsequently structured in order to form semiconductor structures alike transistors, capacitors and resistors. This results in an uneven surface of the substrate due to spaces between these semiconductor devices and different heights of the semiconductor devices. Many manufacturing steps, for example wiring of the semiconductor devices, demand for even surfaces thus intermediate steps for planarizing the structured surfaces are necessary.
U.S. Pat. No. 6,048,475 teaches a method of filling up narrow spaces having a high aspect ratio with several layers comprising a doped silicate glass wherein a lower layer close to a substrate has a high concentration of boron and subsequently deposited layers a lower boron concentrations. Excess silicate glass is removed by a final mechanical chemical polishing (CMP) step.
With reference to FIG. 1 essential characteristics of a CMP will be explained. A semiconductor structure 2 is arranged in a first region 301 of a main surface of a substrate 1 and no structures in a second region 302. In order to planarize this step like surface this arrangement is covered with a silicon glass layer 3 and subsequently a CMP step is applied. The planarity of the remaining structure is improved (FIG. 2). However, the obtained planarity does not meet the requirements of present semiconductor manufacturing steps as the level of the surface in the second region 302 is lower than in the first region.
U.S. Pat. No. 6,146,975 teaches a method of forming a planar wafer by a chemical mechanical polishing. Two kinds of stop layers are applied to the structured surface prior the CMP in order to compensate for different removal rates of the CMP. The stop layers need to be structured by lithographic and etch steps.
U.S. Pat. No. 6,248,667 B1 teaches a method of forming a planar surface using two polishing stop layers wherein a first CMP step is terminated when uncovering the upper of the two polishing stop layers, afterwards the upper polishing stop layer is removed by an etch step, and a subsequent second chemical mechanical polishing step is terminated when uncovering the lower polishing stop layer.
It is an object of the present invention to provide a simplified method of treating a surface of a substrate with a reduced amount of necessary processing steps. A further object is to provide a method of treating a surface of a substrate which is indifferent to the distribution of the density of semiconductor structures.
These objects and other objects are achieved by a method with the features of main claim 1.